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1. openc910 openc910 Public

   Forked from XUANTIE-RV/openc910

   OpenXuantie - OpenC910 Core

   Verilog

2. openface openface Public

   Forked from cmusatyalab/openface

   Face recognition with deep neural networks.

   Lua

3. openwifi openwifi Public

   Forked from open-sdr/openwifi

   open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

   C

4. PySpice PySpice Public

   Forked from PySpice-org/PySpice

   PySpice is a Python 3 package to generate and steer SPICE electronic circuit, to simulate them and finally analyse the output using Python.

   Python

5. Pyverilog Pyverilog Public

   Forked from PyHDI/Pyverilog

   Python-based Hardware Design Processing Toolkit for Verilog HDL

   Python

6. riscv-binutils-gdb riscv-binutils-gdb Public

   Forked from pz9115/riscv-binutils-gdb

   RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

   C